1. Field of the Invention
The present invention relates to a data transfer system, and particularly to a data transfer system capable of simultaneously transferring data of multiple words.
2. Description of the Background Art
FIG. 13 is a block diagram showing an example of a conventional data transfer system. In FIG. 13, a data bus 1 having a bit width of 16 bits performs data transfer between registers 2a and 2b, a data memory 4 and a data operation part 5. Each of the registers 2a and 2b can store data of one word (i.e., 16 bits in the example). The registers 2a and 2b directly receive write data transmitted through the data bus 1. Data read from the registers 2a and 2b is sent to the data bus 1 through bus drivers 3a and 3b, respectively. The bus drivers 3a and 3b are controlled by control signals C9 and C10, respectively. To the data bus 1 is connected a data operation part 5. The data operation part 5 forms, for example, a part of a CPU (central processing unit), and can store the data of one word. To the data bus 1 is also connected a data memory 4. The data memory 4 includes memory areas M(0)-M(n) which are n+1 in number, and the data of one word can be stored in each memory area. Therefore, the data memory 4 can store data of n+1 words. In the prior art shown in FIG. 13, the data memory 4 is formed of a RAM (random access memory) which allows read and write.
FIG. 14 is a circuit diagram showing a specific construction of the bus driver 3a in FIG. 13. In the figure, the bus driver 3a includes n-channel MOS transistors 31 and 32 which are connected in series between the data bus 1 and the ground. The transistor 31 has a gate receiving the control signal C9. The transistor 32 has a gate receiving an inverted signal of a read output of the register 2a sent from an inverter IN.
In a bus driver 3a shown in FIG. 14, when the read data of the register 2a is at an H-level, a signal at an L-level, which is an inverted signal of the above read data is applied from the inverter IN to the gate of the transistor 32. Therefore, the transistor 32 is turned on. In this state, when the register 2a is selected and the control signal C9 is activated to be at the H-level, the transistor 31 is turned on. Therefore, a potential of the precharged data bus 1 is pulled down to the ground level through the transistors 31 and 32. That means that the potential of the data bus 1 is brought to the ground level, i.e., the L-level, and the output data of the register 2a is read to the data bus 1. Conversely, when the read data of the register 2a is at the H-level, the signal at the L-level which is an inverted signal thereof is supplied to the gate of the transistor 32. Therefore, the transistor 32 is turned on. In this state, even when the register 2a is selected and the control signal C9 is activated (i.e., brought to the H-level) to turn on the transistor 31, the potential of the precharged data bus 1 is not pulled down to the ground potential through the transistor 32. Therefore, the potential of the data bus 1 remains at the potential set by the precharging, i.e., at the H-level, which means that the output of the register 2a is read to the data bus 1. On the other hand, when the control signal C9 is active (i.e., at the L-level), the transistor 31 is in the OFF state. Therefore, the potential change of the output of the register 2a is not sent to the data bus 1. When the register 2a is not selected and the control signal C9 is inactive, the output data of the register 2a is not read to the data bus 1.
The bus driver 3b in FIG. 13 has the same construction as the bus driver 3a in FIG. 14, and operates in the same manner.
A data transfer operation in the conventional data transfer system shown in FIG. 13 will be described below.
(1) A data transfer operation from the register 2a or 2b to the data memory 4:
It is assumed that the data memory 4 is writable, and arbitrary addresses are selected in this operation. Since the bit width of the data bus 1 and the bit width of one memory area of the data memory 4 are equal to the bit widths of the respective registers 2a and 2b, the output data of the register 2a or 2b is transferred through the bus driver 3a or 3b and the data bus 1 to the data memory 4. In this operation, if the control signal C9 has been activated by a data transfer instruction from the register 2a to the data memory 4, the data read from the register 2a is transferred to the data memory 4 through the bus driver 3a and the data bus 1. On the other hand, if the control signal C10 has been activated by a data transfer instruction from the register 2b to the data memory 4, the data read from the register 2b is transferred to the data memory 4 through the bus driver 3b and the data bus 1.
(2) A data transfer operation from the data memory 4 to the register 2a or 2b:
It is assumed that the data memory 4 is readable, and arbitrary addresses, e.g., of memory areas M(0) and M(1) are selected in this operation. Data of one word read from the memory area M(0) in the data memory 4 is transferred to the register 2a through the data bus 1. Then, data read from the memory area M(1) in the data memory 4 is transferred to the register 2b through the data bus 1.
(3) A data transfer operation to the data operation part 5:
In this operation, data read from an arbitrary memory area in the data memory, data read from the register 2a, or data read from the register 2b is transferred to the data operation part 5 through the data bus 1.
As described above, since each register, the data operation part, the data bus and one memory area in the data memory have the same bit width in the conventional data transfer system, data of only one word can be transferred between each of the registers, the data operation part and the data memory in one operation. Therefore, if there is generated data of multiple words to be transferred, the transfer operation for one word must be repeated, resulting in a disadvantage that the data transfer requires a long time.